1. Field of the Invention
The present invention relates to a display device which includes a circuit configured using a transistor. The present invention particularly relates to a display device using a light emitting element, an electro-optical element such as a liquid crystal element, or the like as a display medium and to a method for driving the display device.
2. Description of the Related Art
In recent years, with the increase of large-scale display devices such as liquid crystal televisions, display devices have been actively developed. In particular, a technique for forming a pixel circuit and a driver circuit including a shift register and the like (hereinafter also referred to as an internal circuit) over the same insulating substrate by using transistors formed of a non-crystalline semiconductor (hereinafter also referred to as amorphous silicon) has been actively developed because the technique greatly contributes to reductions in power consumption and cost. The internal circuit formed over the insulating substrate is connected to a controller IC or the like (hereinafter also referred to as an external circuit) through an FPC or the like, and thus its operation is controlled.
Among the aforementioned internal circuits, a shift register using transistors formed of a non-crystalline semiconductor (hereinafter also referred to as amorphous silicon transistors) has been devised. FIG. 106A shows a structure of a flip-flop included in a conventional shift register (Reference 1: Japanese Published Patent Application No. 2004-157508). The flip-flop of FIG. 106A includes a transistor 11, a transistor 12, a transistor 13, a transistor 14, a transistor 15, a transistor 16, and a transistor 17, and is connected to a signal line 21, a signal line 22, a wiring 23, a signal line 24, a power supply line 25, and a power supply line 26. A start signal, a reset signal, a clock signal, a power supply potential VDD, and a power supply potential VSS are input to the signal line 21, the signal line 22, the signal line 24, the power supply line 25, and the power supply line 26, respectively. An operation period of the flip-flop of FIG. 106A is divided into a set period, a selection period, a reset period, and a non-selection period as shown in a timing chart of FIG. 106B, and most of the operation period is a non-selection period.
Here, the transistor 12 and the transistor 16 are turned on in a non-selection period. Because amorphous silicon is used for semiconductor layers of the transistor 12 and the transistor 16, fluctuation in threshold voltage (Vth) is caused due to deterioration or the like. Specifically, a threshold voltage is increased. In other words, a conventional shift register, in which the transistor 12 and the transistor 16 cannot be turned on due to an increase in threshold voltage, cannot supply VSS to a node 41 and the wiring 23 and causes malfunction.
In order to solve this problem, shift registers which can suppress a shift in threshold voltage of the transistor 12 have been devised in References 2, 3, and 4 (Reference 2: Soo Young Yoon et al., “Highly Stable Integrated Gate Driver Circuit using a-Si III with Dual Pull-down Structure”, SOCIETY FOR INFORMATION DISPLAY 2005 INTERNATIONAL SYMPOSIUM DIGEST OF TECHNICAL PAPERS, Volume XXXVI, pp. 348-351, Reference 3: Binn Kim et al., “a-Si Gate Driver Integration with Time Shared Data Driving”, Proceedings of The 12th International Display Workshops in conjunction with Asia Display 2005, pp. 1073-1076, and Reference 4: Mindoo Chun et al., “Integrated Gate Driver Using Highly Stable a-Si TFT's”, Proceedings of The 12th International Display Workshops in conjunction with Asia Display 2005, pp. 1077-1080). In References 2, 3, and 4, an additional transistor (called a first transistor) is arranged in parallel with the transistor 12 (called a second transistor), and signals inverted with respect to each other are input to gate electrodes of the first transistor and the second transistor in a non-selection period; thus, shifts in threshold voltage of the first transistor and the second transistor are suppressed.
Further, in Reference 5, a shift register, which can suppress a shift in threshold voltage of the transistor 16 as well as the transistor 12, has been devised (Reference 5: Chun-Ching et al., “Integrated Gate Driver Circuit Using a-Si TFT”, Proceedings of The 12th International Display Workshops in conjunction with Asia Display 2005, pp. 1023-1026). In Reference 5, an additional transistor (called a first transistor) is arranged in parallel with the transistor 12 (called a second transistor) and another additional transistor (called a third transistor) is arranged in parallel with the transistor 16 (called a fourth transistor). In a non-selection period, signals inverted with respect to each other are input to gate electrodes of the first transistor and the second transistor, and signals inverted with respect to each other are input to gate electrodes of the third transistor and the fourth transistor; thus, shifts in threshold voltage of the first, second, third, and fourth transistors are suppressed.
Furthermore, in Reference 6, a shift in threshold voltage of the transistor 12 is suppressed by applying an AC pulse to the gate electrode of the transistor 12 (Reference 6: Yong Ho Jang et al., “A-Si TFT Integrated Gate Driver with AC-Driven Single Pull-down Structure”, SOCIETY FOR INFORMATION DISPLAY 2006 INTERNATIONAL SYMPOSIUM DIGEST OF TECHNICAL PAPERS, Volume XXXVII, pp. 208-211).
Note that in each of the display devices in References 7 and 8, the number of signal lines is reduced to one third by using a shift register formed using an amorphous silicon transistor as a scan line driver circuit and inputting a video signal to each of subpixels of R, G, and B through one signal line (Reference 7: Jin Young Choi et al., “A Compact and Cost-efficient TFT-LCD through the Triple-Gate Pixel Structure”, SOCIETY FOR INFORMATION DISPLAY 2006 INTERNATIONAL SYMPOSIUM DIGEST OF TECHNICAL PAPERS, Volume XXXVII, pp. 274-276, and Reference 8: Yong Soon Lee et al., “Advanced TFT-LCD Data Line Reduction Method”, SOCIETY FOR INFORMATION DISPLAY 2006 INTERNATIONAL SYMPOSIUM DIGEST OF TECHNICAL PAPERS, Volume XXXVII, pp. 1083-1086). Thus, in each of the display devices in References 7 and 8, the number of connections between a display panel and a driver IC is reduced.